<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/"><channel><title>DVP on 技术笔记</title><link>https://deguiliu.github.io/tech-notes/tags/dvp/</link><description>Recent content in DVP on 技术笔记</description><generator>Hugo -- 0.168.0</generator><language>zh-cn</language><lastBuildDate>Tue, 25 Aug 2026 08:00:00 +0000</lastBuildDate><atom:link href="https://deguiliu.github.io/tech-notes/tags/dvp/index.xml" rel="self" type="application/rss+xml"/><item><title>DVP 图像输出通路: 像素时序、模块分工与实现边界</title><link>https://deguiliu.github.io/tech-notes/posts/architecture/dvp_image_output_principle/</link><pubDate>Tue, 25 Aug 2026 08:00:00 +0000</pubDate><guid>https://deguiliu.github.io/tech-notes/posts/architecture/dvp_image_output_principle/</guid><description>DVP 输出由并行像素数据、PCLK、HSYNC 和 VSYNC 共同组成，图像经 DDR 与 VIDEO_O 送入 VOC，实际缺口可能位于框架接入层。</description></item></channel></rss>